1. Field of the Invention
The present invention relates to a semiconductor memory apparatus, and in particular to a semiconductor memory apparatus containing fuses for storing error address information, chip ID information, data for circuit adjustment, etc.
2. Description of the Background Art
Semiconductor memory apparatuses, such as DRAM, SRAM, and FeRAM (Ferroelectric RAM), may include a plurality of fuses so as to non-volatilely store error address information used to correct errors, chip ID information, data for circuit adjustment, etc. To verify whether the fuses are disconnected properly, it is desirable that the data stored in the fuses (hereinafter referred to as the “fuse data”) be easily accessible from the outside of the semiconductor memory apparatus. In addition, it is desirable that fuse data, such as chip ID information, be able to be referred to not only at the time of manufacturing test of the semiconductor memory apparatus but also at the time of normal operation of the semiconductor memory apparatus.
FIG. 19 is a diagram illustrating a configuration of a conventional semiconductor memory apparatus containing fuses, which is described in Japanese Laid-Open Patent Publication No. 2001-351395. The semiconductor memory apparatus shown in FIG. 19 includes I/O terminals 90, memory cell arrays 91, a DQ sense amplifier 92, fuses 93, first latches 94, second latches 95, a read control circuit 96, and test terminals 97. Reading and writing of data from/to the memory cell arrays 91 are performed through the I/O terminals 90. Fuse data stored in a fuse 93 is read by using a corresponding first latch 94, a corresponding second latch 95, and the read control circuit 96. More specifically, the data read from the fuse 93 is once transferred to the corresponding first latch 94 and then serially transferred to the corresponding second latch 95 in synchronization with a clock signal CLK. Thereafter, the read control circuit 96 is activated, whereby the fuse data stored in the corresponding second latch 95 is read through a corresponding test terminal 97.
The above-described conventional method, however, requires a data bus and a control circuit which are specially designed to read fuse data, making the circuit design complex and causing an increase in circuit area. In addition, since fuse data is serially transferred, it takes time to access the fuse data. Moreover, since a random access cannot be performed on fuse data, it is necessary to use an access sequence which is different from that used when reading data from a memory cell.